Design Time Optimization for Hardware Watermarking Protection of HDL Designs
نویسندگان
چکیده
منابع مشابه
Design Time Optimization for Hardware Watermarking Protection of HDL Designs
HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spr...
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Intellectual property (IP) reuse based design is one of the most promising techniques to close the so-called design productivity gap. To facilitate better IP reuse, it is desirable to have IPs exchanged in the soft form such as hardware description language (HDL) source codes. However, soft IPs have higher protection requirements than hard IPs and most existing IP protection techniques are not ...
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Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal verification. This thesis proposes a uni...
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ژورنال
عنوان ژورنال: The Scientific World Journal
سال: 2015
ISSN: 2356-6140,1537-744X
DOI: 10.1155/2015/752969